The present invention relates to a recycling A/D converter capable of implementing the A/D converting processing including not less than three steps.
As disclosed in the Japanese Patent publication No. 6-83069 or in the IEEE Journal of Solid-state Circuits, Vol. 25, No. 6, December 1990, pp1328-PP1338, one of this kind of recycling A/D converters is a so-called two step recycling A/D converter which includes a capacitor array circuit (i.e., an array of capacitors), an operational amplifier, a capacitor connected between the input and output terminals of the operational amplifier, and an A/D conversion circuit of a parallel type.
FIG. 11 shows a circuit arrangement of a 2-step recycling A/D converter. An A/D conversion circuit 1 of a parallel type has an input terminal selectively connectable to a signal input terminal 2 or an output terminal of an operational amplifier 3 via a switch S8. A capacitor array circuit 4 comprises a plurality of arrayed capacitors C0 to C7 which have common electrodes respectively connected to a common line 5. The arrayed capacitors C0 to C7 have non-common electrodes respectively connectable via switches S0 to S7 to one of the input terminal of the A/D conversion circuit 1, a reference voltage terminal 6, and a ground terminal GND. The operational amplifier 3 has an inverting input terminal connected to the common line 5. A capacitor CF and a switch S9 are connected in parallel with each other between the input and output terminals of the operational amplifier 3.
In this circuit arrangement, the A/D conversion circuit 1 implements a first step A/D conversion under a condition where the switch S8 is connected to the input terminal of the A/D conversion circuit 1, while the switches S0 to S7 are respectively connected to the input terminal of the A/D conversion circuit 1 and the switch S9 is turned on.
After the first step A/D conversion is completed, the switch S9 is turned off. Respective switches S0 to S7 are shifted to either the reference voltage terminal 6 or the ground terminal GND in accordance with an A/D conversion code resulting from the first step A/D conversion. As a result, the operational amplifier 3 produces an output voltage equivalent to a residue voltage of the first step A/D conversion result. Then, the switch S8 is shifted to the output terminal of the operational amplifier 3. The A/D conversion circuit 1 implements a second step A/D conversion. An adder 7 adds the A/D conversion code of the first step and the A/D conversion code of the second step, thereby producing an A/D conversion output having a resolution higher than that of the A/D conversion circuit 1.
According to the above-described conventional 2-step recycling A/D converter, the circuit scale of the A/D conversion circuit 1 and the capacitor array circuit 4 expands in proportion to the enhancement of resolution (i.e., bit number). This leads to an undesirable increase of the chip size.